Regviz

Microchip Technology /ATSAME70N21B /USBHS /HSTCTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as HSTCTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Microchip Technology/ATSAMV71J21/USBHS/HSTCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SOFE)SOFE 0 (RESET)RESET 0 (RESUME)RESUME 0 (NORMAL)SPDCONF

SPDCONF=NORMAL

Description

Host General Control Register

Fields

SOFE

Start of Frame Generation Enable
RESET

Send USB Reset
RESUME

Send USB Resume
SPDCONF

Mode Configuration

0 (NORMAL): The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable.

1 (LOW_POWER): For a better consumption, if high speed is not needed.

2 (HIGH_SPEED): Forced high speed.

3 (FORCED_FS): The host remains in Full-speed mode whatever the peripheral speed capability.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data